18125G394ZAT2A [KYOCERA AVX]
Ceramic Capacitor, Multilayer, Ceramic, 50V, 80% +Tol, 20% -Tol, Y5V, -82/+22% TC, 0.39uF, Surface Mount, 1812, CHIP;型号: | 18125G394ZAT2A |
厂家: | KYOCERA AVX |
描述: | Ceramic Capacitor, Multilayer, Ceramic, 50V, 80% +Tol, 20% -Tol, Y5V, -82/+22% TC, 0.39uF, Surface Mount, 1812, CHIP |
文件: | 总21页 (文件大小:322K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Y5V Dielectric
General Specifications
Y5V formulations are for general-purpose use in a limited
temperature range. They have a wide temperature character-
istic of +22% –82% capacitance change over the operating
temperature range of –30°C to +85°C.
Y5V’s high dielectric constant allows the manufacture of the
highest capacitance value in a given case size.
These characteristics make Y5V ideal for decoupling applica-
tions within limited temperature range.
PART NUMBER (see page 3 for complete part number explanation)
0805
3
G
104
Z
A
T
2
A
Size
(L" x W")
Voltage
10V = Z
16V = Y
25V = 3
50V = 5
Dielectric
Y5V = G
Capacitance Capacitance
Failure
Rate
A = Not
Applicable
Terminations
T = Plated Ni
and Solder
Packaging
2 = 7" Reel
4 = 13" Reel
Special
Code
A = Std.
Product
Code
Tolerance
Z = +80 –20%
PERFORMANCE CHARACTERISTICS
Capacitance Range
2200 pF to 22 µF
+80 –20%
Capacitance Tolerances
Operating Temperature Range
Temperature Characteristic
Voltage Ratings
–30°C to +85°C
+22% to –82% max. within operating temperature
10, 16, 25 and 50 VDC (+85°C)
Dissipation Factor
For 50 volts: 5.0% max.
For 16 and 25 volts: 7% max.
For 10 volts: 10% max.
Insulation Resistance (+25°C, RVDC)
Dielectric Strength
Test Voltage
10,000 megohms min. or 1000 MΩ - µF min., whichever is less
250% of rated voltage for 5 seconds at 50 mamp max. current
1.0 Vrms 0.2 Vrms
1 KHz
Test Frequency
16
Y5V Dielectric
Typical Characteristic Curves**
0.1 F - 0603
Impedance vs. Frequency
Temperature Coefficient
10,000
1,000
+20
+10
0
-10
100
10
1
-20
-30
-40
-50
-60
-70
-80
0.1
0.01
10,000
-55 -35
+125
100,000
10,000,000
-15 +5 +25 +45 +65 +85 +105
1,000,000
Frequency (Hz)
Temperature °C
0.22 F - 0805
Impedance vs. Frequency
Capacitance Change
vs. DC Bias Voltage
1,000
100
10
+40
+20
0
-20
-40
-60
-80
-100
1
0.1
0.01
10,000
100,000
1,000,000
10,000,000
0
20
40
60
100
80
Frequency (Hz)
DC Bias Voltage
Insulation Resistance vs. Temperature
1 F - 1206
Impedance vs. Frequency
10,000
1,000
100
1,000
100
10
1
0.1
0
0.01
10,000
+20
+30
+40 +50
+60 +70 +80 +85
100,000
1,000,000
10,000,000
Temperature °C
Frequency (Hz)
SUMMARY OF CAPACITANCE RANGES VS. CHIP SIZE
Style
0402*
0603*
0805*
1206*
1210*
1812*
1825*
2220
10V
2.2nF - 0.1µF
2.2nF - 1µF
10nF - 4.7µF
10nF - 10µF
10nF - 22µF
→
16V
2.2nF - 0.1µF
2.2nF - 0.33µF
10nF - 2.2µF
10nF - 4.7µF
0.1µF - 10µF
→
25V
2.2nF - 22nF
50V
2.2nF - 10nF
2.2nF - 56nF
10nF - 0.33µF
10nF - 1µF
2.2nF - 0.22µF
10nF - 1µF
10nF - 2.2µF
0.1µF - 4.7µF
0.15µF - 1.5µF
0.47µF - 1.5µF
—
0.1µF - 1µF
1.5nF - 1.5µF
0.47µF - 1.5µF
1µF - 1.5µF
0.68µF - 1.5µF
→
→
—
—
2225
→
→
0.68µF - 2.2µF
* Standard Sizes
** For additional information on performance changes with operating conditions consult AVX’s software SpiCap.
17
Y5V Dielectric
Capacitance Range
PREFERRED SIZES ARE SHADED
SIZE
0402*
0603*
0805
1206
1210
1812*
1825*
2220*
2225*
Standard Reel
Packaging
All Paper
All Paper
Paper/Embossed Paper/Embossed Paper/Embossed All Embossed
All Embossed
All Embossed
All Embossed
MM
(in.)
1.00 .10
(.040 .004)
1.60 .15
(.063 .006)
2.01 .20
(.079 .008)
3.20 .20
(.126 .008)
3.20 .20
(.126 .008)
4.50 .30
(.177 .012)
4.50 .30
(.252 .016)
5.7 0.4
(.225 .016)
5.72 .25
(.225 .010)
(L) Length
MM
(in.)
.50 .10
(.020 .004)
.81 .15
(.032 .006)
1.25 .20
(.049 .008)
1.60 .20
(.063 .008)
2.50 .20
(.098 .008)
3.20 .20
(.126 .008)
6.40 .40
(.252 .016)
5.0 0.4
(.197 .016)
6.35 .25
(.250 .010)
(W) Width
MM
(in.)
.60
(.024)
.90
(.035)
1.30
(.051)
1.50
(.059)
1.70
(.067)
1.70
(.067)
1.70
(.067)
2.30
(.090)
1.70
(.067)
(T) Max. Thickness
MM
(in.)
.25 .15
.35 .15
.50 .25
.50 .25
.50 .25
.61 .36
.61 .36
.64 .39
.64 .39
(t) Terminal
WVDC
(.010 .006)
(.014 .006)
(.020 .010)
(.020 .010)
(.020 .010)
(.024 .014)
(.024 .014)
(.025 .015)
(.025 .015)
16 25 50
25
50
25
50
50
25
50
10 16 25 50 10 16 25 50 10 16 25 50 10 16 25 50 10
Cap
(pF)
2200
2700
3300
W
L
᭢
T
3900
4700
5600
᭢
6800
8200
t
Cap
(µF)
.01
.012
.015
.018
.022
.027
.033
.039
.047
.056
.068
.082
.10
.12
.15
.18
.22
.27
.33
.39
.47
.56
.68
.82
1.0
1.2
1.5
1.8
2.2
2.7
3.3
3.9
4.7
5.6
6.8
8.2
10.0
12.0
15.0
18.0
22.0
*Reflow soldering only.
= Paper Tape
= Embossed Tape
NOTES: For low profile product, see page 19.
18
Basic Capacitor Formulas
I. Capacitance (farads)
XI. Equivalent Series Resistance (ohms)
.224 K A
E.S.R. = (D.F.) (Xc) = (D.F.) / (2 π fC)
English: C =
TD
XII. Power Loss (watts)
.0884 K A
2
Metric: C =
Power Loss = (2 π fCV ) (D.F.)
TD
XIII. KVA (Kilowatts)
II. Energy stored in capacitors (Joules, watt - sec)
-3
2
KVA = 2 π fCV x 10
2
1
E = ⁄
2
CV
XIV. Temperature Characteristic (ppm/°C)
III. Linear charge of a capacitor (Amperes)
6
Ct – C25
C25 (Tt – 25)
dV
dt
T.C. =
x 10
I = C
XV. Cap Drift (%)
IV. Total Impedance of a capacitor (ohms)
C1 – C2
C1
2
2
ͱ
C.D. =
x 100
Z = RS + (X - X )
C
L
V. Capacitive Reactance (ohms)
XVI. Reliability of Ceramic Capacitors
1
x =
c
L0
Lt
Vt
Vo
X
Tt
To
Y
=
2 π fC
( ) ( )
VI. Inductive Reactance (ohms)
XVII. Capacitors in Series (current the same)
xL = 2 π fL
Any Number:
1
C
1
1
C2
1
---
=
+
VII. Phase Angles:
C1
C
N
T
Ideal Capacitors: Current leads voltage 90°
Ideal Inductors: Current lags voltage 90°
Ideal Resistors: Current in phase with voltage
C1 C2
C1 + C2
Two: C =
T
XVIII. Capacitors in Parallel (voltage the same)
VIII. Dissipation Factor (%)
C = C1 + C2 --- + C
T
N
E.S.R.
D.F.= tan ␦ (loss angle) =
= (2 πfC) (E.S.R.)
X
XIX. Aging Rate
c
IX. Power Factor (%)
A.R. = %D C/decade of time
P.F. = Sine ␦ (loss angle) = Cos (phase angle)
P.F. = (when less than 10%) = DF
f
XX. Decibels
db = 20 log
V1
V2
X. Quality Factor (dimensionless)
1
D.F.
Q = Cotan ␦ (loss angle) =
METRIC PREFIXES SYMBOLS
-12
K
A
TD
V
t
= Dielectric Constant
= Area
f
= frequency
= Inductance
= Loss angle
= Phase angle
Lt
= Test life
Pico
Nano
Micro
Milli
Deci
Deca
Kilo
Mega
Giga
Tera
X 10
X 10
X 10
X 10
X 10
X 10
X 10
X 10
X 10
X 10
-9
L
␦
Vt
Vo
Tt
= Test voltage
-6
-3
= Dielectric thickness
= Voltage
= Operating voltage
= Test temperature
= Operating temperature
-1
+1
+3
+6
+9
+12
f
= time
X & Y = exponent effect of voltage and temp.
To
R
= Series Resistance
Lo
= Operating life
s
2
How to Order
Part Number Explanation
EXAMPLE: 08055A101JAT2A
0805
5
A
101
J
A
T
2
A
Size
(L" x W")
0402
0504
0603
0805
1005
0907
1206
1210
1505
1805
1808
1812
1825
2225
3640
Dielectric
C0G (NP0) = A
X7R = C
Capacitance
Tolerance
C = .25 pF*
D = .50 pF*
F = 1% (≥ 25 pF)
G = 2% (≥ 13 pF)
J = 5%
K = 10%
M = 20%
Z = +80%, -20%
P = +100%, -0%
Terminations
Special**
Code
Standard:
T = Ni and Tin
Plated
A = Standard
Product
X5R = D
Z5U = E
Y5V = G
Non-Standard
P = Embossed
unmarked
M = Embossed
marked
E = Standard
packaging
Others:
7 = Plated Ni
Gold Plated
1 = Pd/Ag
marked
Low Profile
Chips Only
Max. Thickness
T = .66mm (.026")
S = .56mm (.022")
R = .46mm (.018")
Voltage
10V = Z
Capacitance
Code
Failure
Rate
A = Not
Applicable
16V = Y
(2 significant
digits + no. of
zeros)
25V = 3
50V = 5
100V = 1
200V = 2
250V = V
500V = 7
600V = C
1000V = A
1500V = S
2000V = G
2500V = W
3000V = H
4000V = J
5000V = K
Examples:
Packaging**
10 pF = 100
100 pF = 101
1,000 pF = 102
Recommended:
2 =7" Reel
4 =13" Reel
22,000 pF = 223
220,000 pF = 224
1 µF = 105
Others:
7 = Bulk Cassette
9 = Bulk
For values below 10 pF,
use “R” in place of
decimal point, e.g., 9.1
pfd = 9R1.
*C&D tolerances for Յ10 pF values.
** Standard Tape and Reel material depends upon chip size and thickness.
See individual part tables for tape material type for each capacitance value.
Note: Unmarked product is standard. Marked product is available on special request, please contact AVX.
Standard packaging is shown in the individual tables.
Non-standard packaging is available on special request, please contact AVX.
3
General Specifications
Environmental
MOISTURE RESISTANCE
Specification
THERMAL SHOCK
Specification
Appearance
No visual defects
Appearance
No visual defects
Capacitance Variation
C0G (NP0): 2.5% or .25pF, whichever is greater
X7R: ≤ 7.5%
Capacitance Variation
C0G (NP0): 5% or .5pF, whichever is greater
X7R: ≤ 10%
Z5U: ≤ 20%
Z5U: ≤ 30%
Y5V: ≤ 20%
Y5V: ≤ 30%
Q, Tan Delta
Q, Tan Delta
To meet initial requirement
C0G (NP0):≥ 30pF........................Q ≥ 350
≥ 10pF, < 30pF...........Q ≥ 275+5C/2
< 10pF ........................Q ≥ 200+10C
X7R: Initial requirement + .5%
Z5U: Initial requirement + 1%
Y5V: Initial requirement + 2%
Insulation Resistance
C0G (NP0), X7R: To meet initial requirement
Z5U, Y5V: ≥ Initial Value x 0.1
Dielectric Strength
No problem observed
Insulation Resistance
≥ Initial Value x 0.3
Measuring Conditions
Step
Temperature °C
Time (minutes)
Measuring Conditions
C0G (NP0), X7R: -55° 2°
Z5U: +10° 2°
1
30
3
Step
Temp. °C
Humidity % Time (hrs)
Y5V: -30° 2°
1
+25->+65
+65
+65->+25
+25->+65
+65
+65->+25
+25
90-98
90-98
2.5
3.0
2.5
2.5
3.0
2.5
2.0
–
2
3
Room Temperature
C0G (NP0), X7R: +125° 2°
Z5U, Y5V: +85° 2°
# 3
30
# 3
2
3
80-98
3
4
90-98
4
Room Temperature
5
90-98
6
80-98
Repeat for 5 cycles and measure after 48 hours 4 hours
(24 hours for C0G (NP0)) at room temperature.
7
90-98
7a
7b
-10
+25
uncontrolled
90-98
–
IMMERSION
Specification
Repeat 20 cycles (1-7) and store for 48 hours (24 hours
for C0G (NP0)) at room temperature before measuring.
Steps 7a & 7b are done on any 5 out of first 9 cycles.
Appearance
No visual defects
Capacitance Variation
C0G (NP0): 2.5% or .25pF, whichever is greater
X7R: ≤ 7.5%
Z5U: ≤ 20%
Y5V: ≤ 20%
Q, Tan Delta
To meet initial requirement
Insulation Resistance
C0G (NP0), X7R: To meet initial requirement
Z5U, Y5V: ≥ Initial Value x 0.1
Dielectric Strength
No problem observed
Measuring Conditions
Step
Temperature °C
Time (minutes)
+65 +5/-0
Pure Water
1
15
2
0
3
2
15
2
NaCl solution
Repeat cycle 2 times and wash with water and dry.
Store at room temperature for 48 4 hours (24 hours for
C0G (NP0)) and measure.
22
General Specifications
Environmental
STEADY STATE HUMIDITY
(No Load)
Insulation Resistance
C0G (NP0), X7R: To meet initial value x 0.3
Z5U, Y5V: ≥ Initial Value x 0.1
Specification
Charge devices with rated voltage in test chamber set
Appearance
at 85
5% relative humidity and 85°C for 1000
No visual defects
(+48,-0) hours. Remove from test chamber and
Capacitance Variation
C0G (NP0): 5% or .5pF, whichever is greater
X7R: ≤ 10%
stabilize at room temperature and humidity for 48
hours (24 2 hours for C0G (NP0)) before measuring.
4
Charge and discharge currents must be less than
50ma.
Z5U: ≤ 30%
Y5V: ≤ 30%
Q, Tan Delta
C0G (NP0): ≥ 30pF......................Q ≥ 350
≥ 10pF, < 30pF.........Q ≥ 275+5C/2
< 10pF ....................Q ≥ 200+10C
X7R: Initial requirement + .5%
Z5U: Initial requirement + 1%
Y5V: Initial requirement + 2%
LOAD LIFE
Specification
Appearance
No visual defects
Insulation Resistance
≥ Initial Value x 0.3
Capacitance Variation
C0G (NP0): 3% or .3pF, whichever is greater
X7R: ≤ 10%
Measuring Conditions
Z5U: ≤ 30%
Y5V: ≤ 30%
Store at 85 5% relative humidity and 85°C for 1000
hours, without voltage. Remove from test chamber
and stabilize at room temperature and humidity for
48 4 hours (24 2 hours for C0G (NP0)) before
measuring.
Q, Tan Delta
C0G (NP0): ≥ 30pF......................Q ≥ 350
≥ 10pF, < 30pF.........Q ≥ 275+5C/2
< 10pF ....................Q ≥ 200+10C
X7R: Initial requirement + .5%
Z5U: Initial requirement + 1%
Y5V: Initial requirement + 2%
Charge and discharge currents must be less than
50ma.
Insulation Resistance
C0G (NP0), X7R: To meet initial value x 0.3
Z5U, Y5V: ≥ Initial Value x 0.1
LOAD HUMIDITY
Specification
Charge devices with twice rated voltage in test
chamber set at +125°C 2°C for C0G (NP0) and X7R,
+85° 2°C for Z5U, and Y5V for 1000 (+48,-0) hours.
Remove from test chamber and stabilize at room
temperature for 48 4 hours (24 2 hours for C0G
(NP0)) before measuring.
Appearance
No visual defects
Capacitance Variation
C0G (NP0): 5% or .5pF, whichever is greater
X7R: ≤ 10%
Z5U: ≤ 30%
Y5V: ≤ 30%
Charge and discharge currents must be less than
50ma.
Q, Tan Delta
C0G (NP0): ≥ 30pF .....................Q ≥ 350
≥ 10pF,< 30pF.........Q ≥ 275+5C/2
< 10pF ....................Q ≥ 200+10C
X7R: Initial requirement + .5%
Z5U: Initial requirement + 1%
Y5V: Initial requirement + 2%
23
General Specifications
Mechanical
END TERMINATION ADHERENCE
BEND STRENGTH
Specification
Speed = 1mm/sec
No evidence of peeling of end terminal
2mm
Deflection
Measuring Conditions
R340mm
After soldering devices to circuit board apply 5N
(0.51kg f) for 10 1 seconds, please refer to Figure 1.
Supports
45mm
45mm
5N FORCE
Figure 2. Bend Strength
Specification
Appearance:
DEVICE UNDER TEST
Figure 1.
Terminal Adhesion
No visual defects
TEST BOARD
Capacitance Variation
C0G (NP0): 5% or .5pF, whichever is larger
X7R: ≤ 12%
RESISTANCE TO VIBRATION
Specification
Z5U: ≤ 30%
Y5V: ≤ 30%
Appearance:
No visual defects
Insulation Resistance
C0G (NP0): ≥ Initial Value x 0.3
X7R: ≥ Initial Value x 0.3
Z5U: ≥ Initial Value x 0.1
Y5V: ≥ Initial Value x 0.1
Capacitance
Within specified tolerance
Q, Tan Delta
To meet initial requirement
Measuring Conditions
Please refer to Figure 2
Insulation Resistance
C0G (NP0), X7R Ն Initial Value x 0.3
Z5U, Y5V Ն Initial Value x 0.1
Deflection:
2mm
Measuring Conditions
Test Time:
30 seconds
Vibration Frequency
10-2000 Hz
RESISTANCE TO SOLDER HEAT
Maximum Acceleration
20G
Specification
Swing Width
Appearance:
No serious defects, <25% leaching of either end
terminal
1.5mm
Test Time
X, Y, Z axis for 2 hours each, total 6 hours of test
Capacitance Variation
C0G (NP0): 2.5% or 2.5pF, whichever is greater
X7R: ≤ 7.5%
SOLDERABILITY
Specification
Z5U: ≤ 20%
Y5V: ≤ 20%
Ն 95% of each termination end should be covered with
fresh solder
Q, Tan Delta
To meet initial requirement
Measuring Conditions
Insulation Resistance
Dip device in eutectic solder at 230 5°C for
To meet initial requirement
2
.5 seconds
Dielectric Strength
No problem observed
Measuring Conditions
Dip device in eutectic solder at 260°C, for 1 minute.
Store at room temperature for 48 hours (24 hours for
C0G (NP0)) before measuring electrical parameters.
Part sizes larger than 3.20mm x 2.49mm are reheated
at 150°C for 30 5 seconds before performing test.
24
European Detail Specifications
CECC 32 101-801/Chips
Standard European Ceramic Chip Capacitors
PART NUMBER (example)
0805
5
C
103
M
T
T
2
A
Size
(L" x W")
Voltage
50V = 5
100V = 1
200V = 2
Dielectric
1B CG = A
2R1 = C
Capacitance Capacitance Specification Terminations
Marking
Packaging
2 = 7" Reel
4 = 13" Reel
Special
Code
A = Std.
Product
Code
Tolerance
See Dielectrics
C0G, X7R, Y5V
CECC32101-801 T = Plated Ni
and Sn
2F4 = G
RANGE OF APPROVED COMPONENTS
Voltage and Capacitance Range
100V
Case
Size
Dielectric
Type
50V
200V
1BCG
0603
0805
1206
1210
1808
1812
2220
1B CG
1B CG
1B CG
1B CG
1B CG
1B CG
1B CG
0.47pF - 150pF
0.47pF - 560pF
0.47pF - 3.3nF
0.47pF - 4.7nF
0.47pF - 6.8nF
0.47pF - 15nF
0.47pF - 39nF
0.47pF - 120pF
0.47pF - 560pF
0.47pF - 3.3nF
0.47pF - 4.7nF
0.47pF - 6.8nF
0.47pF - 15nF
0.47pF - 39nF
0.47pF - 100pF
0.47pF - 330pF
0.47pF - 1.5nF
0.47pF - 2.7nF
0.47pF - 4.7nF
0.47pF - 10nF
0.47pF - 15nF
2R1
2F4
0603
0805
1206
1210
1808
1812
2220
2R1
2R1
2R1
2R1
2R1
2R1
2R1
10pF - 6.8nF
10pF - 33nF
10pF - 100nF
10pF - 150nF
10pF - 270nF
10pF - 470nF
10pF - 1.2µF
10pF - 6.8nF
10pF - 18nF
10pF - 68nF
10pF - 100nF
10pF - 180nF
10pF - 330nF
10pF - 680nF
10pF - 1.2nF
10pF - 3.3nF
10pF - 18nF
10pF - 27nF
10pF - 47nF
10pF - 100nF
10pF - 220nF
0805
1206
1210
1808
1812
2220
2F4
2F4
2F4
2F4
2F4
2F4
10pF - 100nF
10pF - 330nF
10pF - 470nF
10pF - 560nF
10pF - 1.8µF
10pF - 2.2µF
31
Packaging of Chip Components
Automatic Insertion Packaging
TAPE & REEL QUANTITIES
All tape and reel specifications are in compliance with RS481.
8mm
12mm
Paper or Embossed Carrier
Embossed Only
0805, 1005, 1206,
1210
0504, 0907
1505, 1805,
1808
1812, 1825
2220, 2225
Paper Only
0402, 0603
2,000 or 4,000(1)
10,000
Qty. per Reel/7" Reel
3,000
1,000
4,000
Qty. per Reel/13" Reel
10,000
(1) Dependent on chip thickness. Low profile chips shown on page 27 are 5,000 per reel for 7" reel. 0402 size chips are 10,000 per 7" reels and are
not available on 13" reels. For 3640 size chip contact factory for quantity per reel.
REEL DIMENSIONS
Tape
A
Max.
B*
Min.
D*
Min.
N
Min.
W2
Max.
C
W1
W3
Size(1)
7.9 Min.
(.311)
8.4+–10..00
14.4
8mm
+.060
(.331
)
(.567)
10.9 Max.
(.429)
–0.0
330
(12.992)
1.5
(.059)
13.0 0.20
(.512 .008)
20.2
(.795)
50
(1.969)
11.9 Min.
(.469)
15.4 Max.
(.607)
12.4+–20..00
18.4
(.724)
12mm
+.076
(.488
)
–0.0
Metric dimensions will govern.
English measurements rounded and for reference only.
(1) For tape sizes 16mm and 24mm (used with chip size 3640) consult EIA RS-481 latest revision.
32
Embossed Carrier Configuration
8 & 12mm Tape Only
8 & 12mm Embossed Tape
Metric Dimensions Will Govern
CONSTANT DIMENSIONS
Tape Size
D0
E
P0
P2
T Max.
T1
G1
G2
8mm
and
12mm
8.4+-00..010
1.75 0.10
4.0 0.10
2.0 0.05
0.600
(.024)
0.10
(.004)
Max.
0.75
0.75
+.004
(.059
-0.0
)
(.069 .004) (.157 .004) (.079 .002)
(.030)
(.030)
Min.
Min.
See Note 3
See Note 4
VARIABLE DIMENSIONS
Tape Size
B1
D1
F
P1
R
T2
W
A0 B0 K0
Max.
Min.
Min.
See Note 6 See Note 5
See Note 2
8.0+-00..13
4.55
1.0
3.5 0.05
4.0 0.10
25
2.5 Max
(.098)
8mm
See Note 1
See Note 1
See Note 1
See Note 1
(.315+-..000142
)
(.179)
(.039)
(.138 .002) (.157 .004)
(.984)
8.2
(.323)
1.5
(.059)
5.5 0.05
(.217 .002) (.157 .004)
4.0 0.10
30
(1.181)
6.5 Max.
(.256)
12.0 .30
(.472 .012)
12mm
8.0+-00..13
8mm
1/2 Pitch
4.55
(.179)
1.0
(.039)
3.5 0.05
(.138 .002) 0.79 .004
2.0 0.10
25
(.984)
2.5 Max.
(.098)
(.315+-..000142
)
12mm
Double
Pitch
8.2
(.323)
1.5
(.059)
5.5 0.05
(.217 .002) (.315 .004)
8.0 0.10
30
(1.181)
6.5 Max.
(.256)
12.0 .30
(.472 .012)
NOTES:
1. A0, B0, and K0 are determined by the max. dimensions to the ends of the terminals extending from the component body and/or the body dimensions of the component. The
clearance between the end of the terminals or body of the component to the sides and depth of the cavity (A0, B0, and K0) must be within 0.05 mm (.002) min. and 0.50 mm
(.020) max. The clearance allowed must also prevent rotation of the component within the cavity of not more than 20 degrees (see sketches C & D).
2. Tape with components shall pass around radius “R” without damage. The minimum trailer length (Note 2 Fig. 3) may require additional length to provide R min. for 12 mm
embossed tape for reels with hub diameters approaching N min. (Table 4).
3. G1 dimension is the flat area from the edge of the sprocket hole to either the outward deformation of the carrier tape between the embossed cavities or to the edge of the
cavity whichever is less.
4. G2 dimension is the flat area from the edge of the carrier tape opposite the sprocket holes to either the outward deformation of the carrier tape between the embossed cavity
or to the edge of the cavity whichever is less.
5. The embossment hole location shall be measured from the sprocket hole controlling the location of the embossment.
Dimensions of embossment location and hole location shall be applied independent of each other.
6. B1 dimension is a reference dimension for tape feeder clearance only.
33
Paper Carrier Configuration
8 & 12mm Tape Only
8 & 12mm Paper Tape
Metric Dimensions Will Govern
CONSTANT DIMENSIONS
Tape Size
D0
E
P0
P2
T1
G1
G2
R MIN.
+0.1
8mm
and
12mm
1.5 -0.0
1.75 0.10
4.0 0.10
2.0 0.05
0.10
(.004)
Max.
0.75
(.030)
Min.
0.75
(.030)
Min.
25 (.984)
See Note 2
+.004
-.000
(.059
)
(.069 .004) (.157 .004) (.079 .002)
VARIABLE DIMENSIONS
Tape Size
P1
F
W
A0 B0
See Note 1
T
8.0+-00..13
8mm
4.0 0.10
(.157 .004)
3.5 0.05
(.138 .002)
See Note 3
(.315+-..000142
)
4.0 .010
(.157 .004)
5.5 0.05
(.217 .002)
12.0 0.3
(.472 .012)
12mm
8.0+-00..13
8mm
1/2 Pitch
2.0 0.10
(.079 .004)
3.5 0.05
(.138 .002)
(.315+-..000142
)
12mm
Double
Pitch
8.0 0.10
(.315 .004)
5.5 0.05
(.217 .002)
12.0 0.3
(.472 .012)
NOTES:
1. A0, B0, and T are determined by the max. dimensions to the ends of the terminals extending from the component body and/or the body dimensions of the component. The
clearance between the ends of the terminals or body of the component to the sides and depth of the cavity (A0, B0, and T) must be within 0.05 mm (.002) min. and 0.50 mm
(.020) max. The clearance allowed must also prevent rotation of the component within the cavity of not more than 20 degrees (see sketches A & B).
2. Tape with components shall pass around radius “R” without damage.
3. 1.1 mm (.043) Base Tape and 1.6 mm (.063) Max. for Non-Paper Base Compositions.
Bar Code Labeling Standard
AVX bar code labeling is available and follows latest version of EIA-556-A.
34
Bulk Case Packaging
BENEFITS
BULK FEEDER
• Easier handling
• Smaller packaging volume
(1/20 of T/R packaging)
• Easier inventory control
• Flexibility
Case
Cassette
• Recyclable
Gate
Shooter
CASE DIMENSIONS
Shutter
Slider
12mm
36mm
Mounter
Head
Expanded Drawing
110mm
Chips
Attachment Base
CASE QUANTITIES
Part Size
0402
0603
0805
Qty.
(pcs / cassette)
10,000 (T=0.6mm)
5,000 (T¯≥0.6mm)
80,000
15,000
35
General Description
Basic Construction – A multilayer ceramic (MLC) capaci-
tor is a monolithic block of ceramic containing two sets of
offset, interleaved planar electrodes that extend to two
opposite surfaces of the ceramic dielectric. This simple
structure requires a considerable amount of sophistication,
both in material and manufacture, to produce it in the quality
and quantities needed in today’s electronic equipment.
Electrode
Ceramic Layer
End Terminations
Terminated
Edge
Terminated
Edge
Margin
Electrodes
Formulations – Multilayer ceramic capacitors are available
in both Class 1 and Class 2 formulations. Temperature
compensating formulation are Class 1 and temperature
stable and general application formulations are classified
as Class 2.
Class 2 – EIA Class 2 capacitors typically are based on the
chemistry of barium titanate and provide a wide range of
capacitance values and temperature stability. The most
commonly used Class 2 dielectrics are X7R and Y5V. The
X7R provides intermediate capacitance values which vary
only 15% over the temperature range of -55°C to 125°C. It
finds applications where stability over a wide temperature
range is required.
Class 1 – Class 1 capacitors or temperature compensating
capacitors are usually made from mixtures of titanates
where barium titanate is normally not a major part of the
mix. They have predictable temperature coefficients and
in general, do not have an aging characteristic. Thus they
are the most stable capacitor available. The most popular
Class 1 multilayer ceramic capacitors are C0G (NP0)
temperature compensating capacitors (negative-positive
0 ppm/°C).
The Y5V provides the highest capacitance values and is
used in applications where limited temperature changes are
expected. The capacitance value for Y5V can vary from
22% to -82% over the -30°C to 85°C temperature range.
The Z5U dielectric is between X7R and Y5V in both stability
and capacitance range.
All Class 2 capacitors vary in capacitance value under the
influence of temperature, operating voltage (both AC and
DC), and frequency. For additional information on perfor-
mance changes with operating conditions, consult AVX’s
software, SpiCap.
36
General Description
Effects of Voltage – Variations in voltage have little effect
on Class 1 dielectric but does affect the capacitance and
dissipation factor of Class 2 dielectrics. The application of
DC voltage reduces both the capacitance and dissipation
factor while the application of an AC voltage within a
reasonable range tends to increase both capacitance and
dissipation factor readings. If a high enough AC voltage is
applied, eventually it will reduce capacitance just as a DC
voltage will. Figure 2 shows the effects of AC voltage.
Cap. Change vs. D.C. Volts
AVX X7R T.C.
2.5
0
-2.5
-5
-7.5
-10
Cap. Change vs. A.C. Volts
AVX X7R T.C.
25%
50%
Percent Rated Volts
Figure 4
75%
100%
50
40
30
20
Typical Cap. Change vs. Temperature
AVX X7R T.C.
+20
+10
0
10
0
0VDC
RVDC
12.5
25
37.5
50
Volts AC at 1.0 KHz
Figure 2
-10
Capacitor specifications specify the AC voltage at which to
measure (normally 0.5 or 1 VAC) and application of the
wrong voltage can cause spurious readings. Figure 3 gives
the voltage coefficient of dissipation factor for various AC
voltages at 1 kilohertz. Applications of different frequencies
will affect the percentage changes versus voltages.
-20
-30
-55 -35 -15 +5 +25 +45 +65 +85 +105 +125
Temperature Degrees Centigrade
Figure 5
D.F. vs. A.C. Measurement Volts
AVX X7R T.C.
Effects of Time – Class 2 ceramic capacitors change
capacitance and dissipation factor with time as well as tem-
perature, voltage and frequency. This change with time is
known as aging. Aging is caused by a gradual re-alignment
of the crystalline structure of the ceramic and produces an
exponential loss in capacitance and decrease in dissipation
factor versus time. A typical curve of aging rate for semi-
stable ceramics is shown in Figure 6.
10.0
Curve 1 - 100 VDC Rated Capacitor
Curve 2 - 50 VDC Rated Capacitor
Curve 3 - 25 VDC Rated Capacitor
Curve 3
Curve 2
8.0
6.0
4.0
If a Class 2 ceramic capacitor that has been sitting on the
shelf for a period of time, is heated above its curie point,
Curve 1
2.0
0
1
(125°C for 4 hours or 150°C for ⁄
2
hour will suffice) the part
will de-age and return to its initial capacitance and dissi-
pation factor readings. Because the capacitance changes
rapidly, immediately after de-aging, the basic capacitance
measurements are normally referred to a time period some-
time after the de-aging process. Various manufacturers use
different time bases but the most popular one is one day
or twenty-four hours after “last heat.” Change in the aging
curve can be caused by the application of voltage and
other stresses. The possible changes in capacitance due to
de-aging by heating the unit explain why capacitance
changes are allowed after test, such as temperature cycling,
moisture resistance, etc., in MIL specs. The application of
high voltages such as dielectric withstanding voltages also
.5
1.0
1.5
2.0
2.5
AC Measurement Volts at 1.0 KHz
Figure 3
The effect of the application of DC voltage is shown in
Figure 4. The voltage coefficient is more pronounced for
higher K dielectrics. These figures are shown for room tem-
perature conditions. The combination characteristic known
as voltage temperature limits which shows the effects of
rated voltage over the operating temperature range is
shown in Figure 5 for the military BX characteristic.
37
General Description
tends to de-age capacitors and is why re-reading of capac-
itance after 12 or 24 hours is allowed in military specifica-
tions after dielectric strength tests have been performed.
Effects of Mechanical Stress – High “K” dielectric
ceramic capacitors exhibit some low level piezoelectric
reactions under mechanical stress. As a general statement,
the piezoelectric output is higher, the higher the dielectric
constant of the ceramic. It is desirable to investigate this
effect before using high “K” dielectrics as coupling capaci-
tors in extremely low level applications.
Typical Curve of Aging Rate
X7R Dielectric
+1.5
0
Reliability – Historically ceramic capacitors have been one
of the most reliable types of capacitors in use today.
The approximate formula for the reliability of a ceramic
capacitor is:
-1.5
Lo
Lt
Vt
X
Tt
Y
=
͑ ͑
͑ ͑
V
T
o
o
-3.0
-4.5
where
Lo = operating life
Lt = test life
Vt = test voltage
Tt = test temperature and
To = operating temperature
in °C
Vo = operating voltage
X,Y = see text
-6.0
-7.5
Historically for ceramic capacitors exponent X has been
considered as 3. The exponent Y for temperature effects
typically tends to run about 8.
1
10
100 1000 10,000 100,000
Hours
Characteristic Max. Aging Rate %/Decade
None
C0G (NP0)
X7R
Z5U
A capacitor is a component which is capable of storing
electrical energy. It consists of two conductive plates (elec-
trodes) separated by insulating material which is called the
dielectric. A typical formula for determining capacitance is:
2
3
5
Y5V
Figure 6
.224 KA
Effects of Frequency – Frequency affects capacitance
and impedance characteristics of capacitors. This effect is
much more pronounced in high dielectric constant ceramic
formulation that is low K formulations. AVX’s SpiCap soft-
ware generates impedance, ESR, series inductance, series
resonant frequency and capacitance all as functions of fre-
quency, temperature and DC bias for standard chip sizes
and styles. It is available free from AVX.
C =
t
C = capacitance (picofarads)
K = dielectric constant (Vacuum = 1)
A = area in square inches
t = separation between the plates in inches
(thickness of dielectric)
.224 = conversion constant
(.0884 for metric system in cm)
Capacitance – The standard unit of capacitance is the
farad. A capacitor has a capacitance of 1 farad when 1
coulomb charges it to 1 volt. One farad is a very large unit
-6
and most capacitors have values in the micro (10 ), nano
-9
-12
(10 ) or pico (10 ) farad level.
Dielectric Constant – In the formula for capacitance given
above the dielectric constant of a vacuum is arbitrarily cho-
sen as the number 1. Dielectric constants of other materials
are then compared to the dielectric constant of a vacuum.
Dielectric Thickness – Capacitance is indirectly propor-
tional to the separation between electrodes. Lower voltage
requirements mean thinner dielectrics and greater capaci-
tance per volume.
Area – Capacitance is directly proportional to the area of
the electrodes. Since the other variables in the equation are
usually set by the performance desired, area is the easiest
parameter to modify to obtain a specific capacitance within
a material group.
38
General Description
Energy Stored – The energy which can be stored in a
capacitor is given by the formula:
I (Ideal)
I (Actual)
E = 1⁄ CV2
2
Loss
Angle
Phase
Angle
E = energy in joules (watts-sec)
V = applied voltage
␦
C = capacitance in farads
f
Potential Change – A capacitor is a reactive component
which reacts against a change in potential across it. This is
shown by the equation for the linear charge of a capacitor:
V
IRs
dV
dt
In practice the current leads the voltage by some other
phase angle due to the series resistance RS. The comple-
ment of this angle is called the loss angle and:
Iideal
=
C
where
I = Current
C = Capacitance
dV/dt = Slope of voltage transition across capacitor
Power Factor (P.F.) = Cos f or Sine ␦
Dissipation Factor (D.F.) = tan ␦
Thus an infinite current would be required to instantly
change the potential across a capacitor. The amount of
current a capacitor can “sink” is determined by the above
equation.
for small values of ␦ the tan and sine are essentially equal
which has led to the common interchangeability of the two
terms in the industry.
Equivalent Circuit – A capacitor, as a practical device,
exhibits not only capacitance but also resistance and induc-
tance. A simplified schematic for the equivalent circuit is:
Equivalent Series Resistance – The term E.S.R. or
Equivalent Series Resistance combines all losses both
series and parallel in a capacitor at a given frequency so
that the equivalent circuit is reduced to a simple R-C series
connection.
C = Capacitance
L = Inductance
Rp = Parallel Resistance
Rs = Series Resistance
R P
E.S.R.
C
L
R S
Dissipation Factor – The DF/PF of a capacitor tells what
percent of the apparent power input will turn to heat in the
capacitor.
C
Reactance – Since the insulation resistance (Rp) is normally
very high, the total impedance of a capacitor is:
E.S.R.
Dissipation Factor =
= (2 π fC) (E.S.R.)
XC
The watts loss are:
2
2
Z = RS + (XC - XL)
ͱ
Watts loss = (2 π fCV2) (D.F.)
where
Z = Total Impedance
Rs = Series Resistance
XC = Capacitive Reactance =
Very low values of dissipation factor are expressed as their
reciprocal for convenience. These are called the “Q” or
Quality factor of capacitors.
1
2 π fC
Parasitic Inductance – The parasitic inductance of capac-
itors is becoming more and more important in the decou-
pling of today’s high speed digital systems. The relationship
between the inductance and the ripple voltage induced on
the DC voltage line can be seen from the simple inductance
equation:
XL = Inductive Reactance = 2 π fL
The variation of a capacitor’s impedance with frequency
determines its effectiveness in many applications.
Phase Angle – Power Factor and Dissipation Factor are
often confused since they are both measures of the loss in a
capacitor under AC application and are often almost identi-
cal in value. In a “perfect” capacitor the current in the
capacitor will lead the voltage by 90°.
di
dt
V = L
39
General Description
di
dt
is determined by dividing the rated voltage by IR (Ohm’s
Law).
The
seen in current microprocessors can be as high as
0.3 A/ns, and up to 10A/ns. At 0.3 A/ns, 100pH of parasitic
inductance can cause a voltage spike of 30mV. While this
does not sound very drastic, with the Vcc for microproces-
sors decreasing at the current rate, this can be a fairly large
percentage.
Dielectric Strength – Dielectric Strength is an expression
of the ability of a material to withstand an electrical stress.
Although dielectric strength is ordinarily expressed in volts, it
is actually dependent on the thickness of the dielectric and
thus is also more generically a function of volts/mil.
Another important, often overlooked, reason for knowing
the parasitic inductance is the calculation of the resonant
frequency. This can be important for high frequency, by-
pass capacitors, as the resonant point will give the most
signal attenuation. The resonant frequency is calculated
from the simple equation:
Dielectric Absorption – A capacitor does not discharge
instantaneously upon application of a short circuit, but
drains gradually after the capacitance proper has been dis-
charged. It is common practice to measure the dielectric
absorption by determining the “reappearing voltage” which
appears across a capacitor at some point in time after it has
been fully discharged under short circuit conditions.
fres =
1
ͱ
2 LC
Corona – Corona is the ionization of air or other vapors
which causes them to conduct current. It is especially
prevalent in high voltage units but can occur with low voltages
as well where high voltage gradients occur. The energy
discharged degrades the performance of the capacitor and
can in time cause catastrophic failures.
Insulation Resistance – Insulation Resistance is the resis-
tance measured across the terminals of a capacitor and
consists principally of the parallel resistance RP shown in
the equivalent circuit. As capacitance values and hence the
area of dielectric increases, the I.R. decreases and hence
the product (C x IR or RC) is often specified in ohm farads
or more commonly megohm-microfarads. Leakage current
40
Surface Mounting Guide
MLC Chip Capacitors
Component Pad Design
Component pads should be designed to achieve good sol-
der filets and minimize component movement during reflow
soldering. Pad designs are given below for the most com-
mon sizes of multilayer ceramic capacitors for both wave
and reflow soldering. The basis of these designs is:
• Pad width equal to component width. It is permissible to
decrease this to as low as 85% of component width but it
is not advisable to go below this.
• Pad overlap 0.5mm beneath component.
• Pad extension 0.5mm beyond components for reflow and
1.0mm for wave soldering.
REFLOW SOLDERING
Case Size
0402
D1
D2
D3
D4
D5
D2
1.70 (0.07)
2.30 (0.09)
3.00 (0.12)
4.00 (0.16)
4.00 (0.16)
5.60 (0.22)
5.60 (0.22)
5.60 (0.22)
6.60 (0.26)
6.60 (0.26)
0.60 (0.02)
0.80 (0.03)
1.00 (0.04)
1.00 (0.04)
1.00 (0.04)
1.00 (0.04)
1.00 (0.04))
1.00 (0.04)
1.00 (0.04)
1.00 (0.04)
0.50 (0.02)
0.70 (0.03)
1.00 (0.04)
2.00 (0.09)
2.00 (0.09)
3.60 (0.14)
3.60 (0.14)
3.60 (0.14)
4.60 (0.18)
4.60 (0.18)
0.60 (0.02)
0.80 (0.03)
1.00 (0.04)
1.00 (0.04)
1.00 (0.04)
1.00 (0.04)
1.00 (0.04)
1.00 (0.04)
1.00 (0.04)
1.00 (0.04)
0.50 (0.02)
0.75 (0.03)
1.25 (0.05)
1.60 (0.06)
2.50 (0.10)
2.00 (0.08)
3.00 (0.12)
6.35 (0.25)
5.00 (0.20)
6.35 (0.25)
0603
0805
1206
1210
1808
1812
1825
2220
D1
D3
D4
D5
2225
Dimensions in millimeters (inches)
41
Surface Mounting Guide
MLC Chip Capacitors
WAVE SOLDERING
D2
Case Size
0603
D1
D2
D3
D4
D5
3.10 (0.12)
4.00 (0.15)
5.00 (0.19)
5.00 (0.19)
1.20 (0.05)
1.50 (0.06)
1.50 (0.06)
1.50 (0.06)
0.70 (0.03)
1.00 (0.04)
2.00 (0.09)
2.00 (0.09)
1.20 (0.05)
1.50 (0.06)
1.50 (0.06)
1.50 (0.06)
0.75 (0.03)
1.25 (0.05)
1.60 (0.06)
2.50 (0.10)
D1
D3
D4
0805
1206
1210
D5
Dimensions in millimeters (inches)
Component Spacing
Preheat & Soldering
For wave soldering components, must be spaced sufficiently
far apart to avoid bridging or shadowing (inability of solder
to penetrate properly into small spaces). This is less impor-
tant for reflow soldering but sufficient space must be
allowed to enable rework should it be required.
The rate of preheat should not exceed 4°C/second to
prevent thermal shock. A better maximum figure is about
2°C/second.
For capacitors size 1206 and below, with a maximum
thickness of 1.25mm, it is generally permissible to allow a
temperature differential from preheat to soldering of 150°C.
In all other cases this differential should not exceed 100°C.
For further specific application or process advice, please
consult AVX.
≥1.5mm (0.06)
≥1mm (0.04)
Cleaning
Care should be taken to ensure that the capacitors are
thoroughly cleaned of flux residues especially the space
beneath the capacitor. Such residues may otherwise
become conductive and effectively offer a low resistance
bypass to the capacitor.
≥1mm (0.04)
Ultrasonic cleaning is permissible, the recommended
conditions being 8 Watts/litre at 20-45 kHz, with a process
cycle of 2 minutes vapor rinse, 2 minutes immersion in the
ultrasonic solvent bath and finally 2 minutes vapor rinse.
42
Surface Mounting Guide
MLC Chip Capacitors
General
APPLICATION NOTES
Surface mounting chip multilayer ceramic capacitors
are designed for soldering to printed circuit boards or other
substrates. The construction of the components is such that
they will withstand the time/temperature profiles used in both
wave and reflow soldering methods.
Storage
Good solderability is maintained for at least twelve months,
provided the components are stored in their “as received”
packaging at less than 40°C and 70% RH.
Solderability
Handling
Terminations to be well soldered after immersion in a 60/40
tin/lead solder bath at 235 5°C for 2 1 seconds.
Chip multilayer ceramic capacitors should be handled with
care to avoid damage or contamination from perspiration
and skin oils. The use of tweezers or vacuum pick ups
is strongly recommended for individual components. Bulk
handling should ensure that abrasion and mechanical shock
are minimized. Taped and reeled components provides the
ideal medium for direct presentation to the placement
machine. Any mechanical shock should be minimized during
handling chip multilayer ceramic capacitors.
Leaching
Terminations will resist leaching for at least the immersion
times and conditions shown below.
Solder
Tin/Lead/Silver Temp. °C
60/40/0 260 5
Solder
Immersion Time
Seconds
Termination Type
Nickel Barrier
30 1
Preheat
It is important to avoid the possibility of thermal shock during
soldering and carefully controlled preheat is therefore
required. The rate of preheat should not exceed 4°C/second
and a target figure 2°C/second is recommended. Although
an 80°C to 120°C temperature differential is preferred,
recent developments allow a temperature differential
between the component surface and the soldering temper-
ature of 150°C (Maximum) for capacitors of 1210 size and
below with a maximum thickness of 1.25mm. The user is
cautioned that the risk of thermal shock increases as chip
size or temperature differential increases.
Recommended Soldering Profiles
Reflow
300
Natural
Cooling
Preheat
250
200
220°C
150
100
50
to
250°C
Soldering
Mildly activated rosin fluxes are preferred. The minimum
amount of solder to give a good joint should be used.
Excessive solder can lead to damage from the stresses
caused by the difference in coefficients of expansion
between solder, chip and substrate. AVX terminations are
suitable for all wave and reflow soldering systems. If hand
soldering cannot be avoided, the preferred technique is the
utilization of hot air soldering tools.
0
1min
(Minimize soldering time)
10 sec. max
1min
Wave
Cooling
Natural cooling in air is preferred, as this minimizes stresses
within the soldered joint. When forced air cooling is used,
cooling rate should not exceed 4°C/second. Quenching
is not recommended but if used, maximum temperature
differentials should be observed according to the preheat
conditions above.
300
Preheat
Natural
Cooling
250
200
150
100
50
T
230°C
to
Cleaning
250°C
Flux residues may be hygroscopic or acidic and must be
removed. AVX MLC capacitors are acceptable for use with
all of the solvents described in the specifications MIL-STD-
202 and EIA-RS-198. Alcohol based solvents are acceptable
and properly controlled water cleaning systems are also
acceptable. Many other solvents have been proven successful,
and most solvents that are acceptable to other components
on circuit assemblies are equally acceptable for use with
ceramic capacitors.
0
1 to 2 min
3 sec. max
(Preheat chips before soldering)
T/maximum 150°C
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